There is an increasing demand for non-volatile memory devices which can be electrically programmed and erased. Non-volatile memory devices are widely used in storage media for portable electronic devices, such as digital cameras, digital televisions, personal digital assistants (PDAs), MP3 players, or the like.
To increase storage capacity, a non-volatile memory device such as a NAND flash memory may have multiple stacks of memory dies (e.g., chips) to thereby form a memory die package. The memory die package can be implemented in various forms such as a DDP (Double-Die Package), a QDP (Quad-Die Package), an ODP (Octo-Die Package), or the like, depending on the number of stacks (i.e., dies) included in the memory die package. For example, the ODP may have 8 memory dies that are stacked on a substrate. In such a structure which includes a plurality of stacked memory dies, multiple IO (input/output) channels (e.g., buses) are connected between pads of the multiple memory dies and a pad of one memory controller that may be stacked on top of the stacked memory dies.
FIG. 2 is a side view of prior art embodiment of a memory device having a memory die package and a memory controller. FIG. 3 a top view of the memory device of FIG. 2. As depicted, the memory device 200 includes a memory controller 210, a memory die package 230, and a substrate 250. The memory controller 210 may include an interface module 220 that is configured to communicate with a plurality of stacked memory dies in the memory die package 203, as shown in FIG. 3. The memory die package 230 may have 8 dies (C1 to C8) that are stacked on the substrate 250, thereby forming an ODP. A memory controller 210 may be disposed on a top memory die (i.e., the die C1) of the memory die package 230. A formation of stacking the memory dies may be determined according to various design requirements such as the dimension/size of each memory die. For example, the memory die C8 at the bottom may have the largest dimension and the dimension of the memory dies may become smaller as the memory dies are stacked. As shown in FIG. 2, the die C7 may be stacked on the die C8 in such a way that the die C7 is shifted to a right direction by a particular margin. Each of the memory dies (C1 to C8) is coupled to its adjacent memory dies, and the top die C1 is coupled to the memory controller 210. To this end, as shown in FIG. 3, a pad IO of the memory die C8 is coupled to a pad IO of an adjacent memory die (i.e., C7), and a pad IO of the memory die C7 is coupled to a pad IO of an adjacent memory die (i.e., C6), and so forth. A pad IO of a top die C1 is coupled to a pad IO of the memory controller, as shown in FIG. 3. Coupling the IO pads may be implemented using any circuit element connection technique, such as a wire connection.
However, in the above prior art embodiment, as the number of stacks increases, IO capacitance (e.g., a junction capacitance of a transistor, capacitance of metal lines, capacitance of pads in the memory device, etc.) significantly increases. The increase of capacitance in the memory device may require more current to be consumed during the operation of the memory device. In a memory reading/writing operation of a large-volume of data, current consumption becomes one of several significant factors which determines the memory operation performance. Similar problems arise when other types of die are stacked to form a die package.